The present invention relates to semiconductor design technology, and more particularly to a pad of a semiconductor memory device for inputting/outputting a signal.
In general, semiconductor memory devices include contacts, e.g., pads, for inputting or outputting a variety of signals. Semiconductor memory devices must have predetermined number of pads at least that corresponds to number of kinds of various signals and external supply voltages, which are defined in a standard spec. Besides, semiconductor memory devices further include additional pads for a testing procedure generally. Thus, the additional pads are used for monitoring internally generated voltages of a semiconductor device or applying internal signals from the outside.
FIG. 1 is a block diagram illustrating the arrangement of banks and pads in a conventional semiconductor memory device.
Referring to FIG. 1, the conventional semiconductor memory device includes zeroth to third banks 72, 74, 76 and 78, a data pad unit 10, an internal voltage pad unit 20, a reference voltage pad unit 30, a command pad unit 40, an address pad unit 50, and a power supply pad unit 60. In each of the zeroth to third banks 72, 74, 76 and 78, a plurality of unit memory cells for storing data are arranged in an array form. The data pad unit 10 includes a plurality of pads configured to input/output the corresponding data. The internal voltage pad unit 20 includes a plurality of pads configured to output corresponding internal voltages. The reference voltage pad unit 30 includes a plurality of pads configured to input/output corresponding reference voltages. The command pad unit 40 includes a plurality of pads configured to receive corresponding commands. The address pad unit 50 includes a plurality of pads configured to receive corresponding addresses. The power supply pad 60 includes a plurality of pads configured to receive corresponding driving powers.
Such pads serve as interfaces configured to input/output commands, addresses, data and driving powers of a semiconductor memory device and to measure internal signals of the semiconductor memory device.
Herein, the pad units are disposed between the banks, i.e., between the zeroth and second banks 72 and 76 and between the first and third banks 74 and 78.
FIG. 2 is a block diagram illustrating connections between a voltage generator, the internal voltage pad unit 20 and the reference voltage pad unit 30 of FIG. 1.
Referring to FIG. 2, the conventional semiconductor memory device includes a reference voltage generator 80, an internal voltage generator 90, an internal voltage pad unit 20, a reference voltage pad unit 30, and an internal block 98. The reference voltage generator 80 generates first to fifth reference voltages VREFP, VREFC, VREFE, VREFB and VREFD. The internal voltage generator 90 receives the first to fifth reference voltages VREFP, VREFC, VREFE, VREFB and VREFD to generate corresponding internal voltages VPP, VCORE, VPERI, VBLP, VCP, VBB and VDLL. The internal voltage pad unit 20 includes a plurality of pads configured to output the corresponding internal voltages VPP, VCORE, VPERI, VBLP, VCP, VBB and VDLL. The reference voltage pad unit 30 includes a plurality of pads configured to input/output the first to fifth reference voltages VREFP, VREFC, VREFE, VREFB and VREFD from/to the outside. The internal block 98 is driven by receiving the output voltages VPP, VCORE, VPERI, VBLP, VCP, VBB and VDLL of the internal voltage generator 90.
As for its operation mechanism, the reference voltage generator 80 generates the first to fifth reference voltages VREFP, VREFC, VREFE, VREFB and VREFD. Subsequently, the internal voltage generator 90 receives the first to fifth reference voltages VREFP, VREFC, VREFE, VREFB and VREFD to generate the internal voltages VPP, VCORE, VPERI, VBLP, VCP, VBB and VDLL correspondingly.
Thereafter, each of the pads in the internal voltage pad unit 20 outputs one of the internal voltages VPP, VCORE, VPERI, VBLP, VCP, VBB and VDLL to the outside. Likewise, the pads in the reference voltage pad unit 30 inputs/outputs one of the first to fifth reference voltages VREFP, VREFC, VREFE, VREFB and VREFD from/to the outside. The internal block 98 is driven by receiving the output voltages VPP, VCORE, VPERI, VBLP, VCP, VBB and VDLL of the internal voltage generator 90.
In this manner, the conventional semiconductor memory device respectively includes a plurality of pads for inputting/outputting a plurality of reference voltages and a plurality of pads for outputting internal voltages. In the case where pads are provided for respective voltages, there is a problem in that a chip size must be increased due to a number of the pads.